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Virtual Memory And Paging Essay

635 words - 3 pages

Undergraduate Program
Bachelor of Computer Science (Systems and Networking)

Advanced Operating Systems

Submitted by:

Mohammad Ali – SN094901

Submitted to:

Dr. Mohd Ezanee
Submission date:


(a) Virtual memory can be based on Paging only, Segmentation only or a combination of the

With the help of a diagram, show how a virtual address is translated into a physical
address in a paging-based memory management scheme OR in a segmentation-based
memory management scheme.

The mechanism used for reading a word from memory involves the translation of a virtual
address consisting of page number and offset into a physical address, consisting of frame
number and offset and this translation is done using a page table. Figure 1 shows the structure
of paging mechanism. When a particular process is running, a register holds the starting address
of the page ...view middle of the document...

The basic unit of memory allocation for this technique is page and
the page size is 212 (4096 bytes or 4KB).

(iii) Every virtual memory reference causes two physical memory accesses - to fetch the
appropriate page table entry and to fetch the desired data. Thus, the memory access
time is doubled. What solution do the modern computer architectures provide to this
problem? Explain and illustrate your answer with a diagram.

Most virtual memory schemes make use of a special high-speed cache for page table entries,
usually called a translation lookaside buffer (TLB) to solve the problem of memory access

Figure 2: Use of a Translation Lookaside Buffer

time. This cache functions in the same way as a memory cache and contains the page table
entries that have been most recently used. From figure 2 illustrate the use of TLB. Given a

virtual address, the processor will first examine the TLB. If the desired page table entry is
present (TLB hit), then the frame number is retrieved and the real address is formed. If the
desired page table entry is not found (TLB miss), then the processor uses the page number to
index the process page table and examine the corresponding page table entry. If the “present
bit” is set, then the page is in main memory, and the processor can retrieve the frame number
from the page table entry to form the real address. The processor also updates the TLB to
include this new page table entry. Finally, if the present bit is not set, then the desired page is
not in main memory and a memory access fault, called a page fault, is issued.
(iv) A system that uses a two-level page table has 212– byte pages and 32-bit virtual
addresses. The first 8 bits of the address serve as the index into the first-level page
1. How many bits specify the second-level index?

(32 – 8 – 12) 12 bits

2. How many entries are in a level-one page table?

2^8 entries

3. How many entries are in a level-two page table?

2^12 entries

4. How many pages are in the virtual address space?

2^20 pages

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